BGA (Ball Grid Array) is an advanced type of semiconductor packaging technology which is characterized in the use of a substrate whose front side is mounted with a semiconductor die and whose back side is mounted with a grid array of solder balls. During SMT (Surface Mount Technology) process, the BGA package can be mechanically bonded and electrically coupled to an external printed circuit board (PCB) by means of these solder balls.
Typically, the BGA substrate includes one or two power rings and a ground ring formed on the front side thereof. The power rings are ring-shaped electrically-conductive traces that surround the packaged die and is used to deliver the power from the external PCB to the packaged chip during operation. Additionally, the substrate commonly includes a ground ring comprising a ring-shaped electrically-conductive trace arranged alongside the power rings. The ground ring is used to connect the ground pads of the packaged die to grounding lines on the external PCB.
Surrounding the power and ground rings are a multiplicity of I/O traces which are used to connect the die to an associated multiplicity of I/O connections. Current industry emphasis on decreased size and increased functionality of semiconductor die has resulted in the continuing development of integrated circuit die having a high density of active circuits. Conventionally, the logic circuitry of the die is formed on the interior portion of the die and a plurality of input/output (I/O) devices or cells are located around the periphery of the die. Each I/O cell, typically, is connected to at least one bond pad fabricated at the surface of the die that serves as the input/output (I/O) contact for that cell.
Commonly, the dies are mounted on a specifically constructed substrate. Power is supplied to the die through a pair of circumferential power rings that surround the die and are located on an inner portion of a front surface of the substrate. Typically, the dies are connected to power rings by a plurality of bond wires. In conventional applications, such dies are limited to only two power voltages (one for each power ring). In some alternative applications, the outer power ring is split into four (4) power sources. Thus, in some implementations, as many as five different voltages can be supplied to a die. This is the upper limit of present technologies. In order to gain access to more than five voltages, I/O contacts must be sacrificed in order to accommodate additional power supply voltage needs. Where many power voltages are required, this causes a serious reduction of the available I/O connections. Additionally, numerous other disadvantageous of the present art will be described hereinbelow.
FIG. 1A shows a very simplified cross-section schematic view a typical BGA package with power ring and ground ring (note that FIG. 1A is simplified schematic diagram showing only a small number of components, the actual BGA structure and circuit layout may be much more complex).
As shown, this BGA package includes: (a) a substrate 100 having a front side 100a and a back side 100b; (b) a ground ring 110 formed on the front side 100a of the substrate 100; (c) a first power ring 120 formed alongside the ground ring 110 and a second power ring 123 formed alongside the first power ring 120; (d) a plurality of I/O pads 130 formed over the front side 100a of the substrate 100; (d) a plurality of vias (electrically-conductive through-holes) 141, 142, 143, 144 penetrating the substrate 100, which include a subgroup of ground vias 141 each having an upper end connected to the ground ring 110 and a bottom end exposed on the back side 100b of the substrate 100; a subgroup of first power vias 142 each having an upper end connected to the first power ring 120 and a bottom end exposed on the back side 100b of the substrate 100; a subgroup of second power vias 143 each having an upper end connected to the second power ring 123 and a bottom end exposed on the back side 100b of the substrate 100; a subgroup of I/O vias 144 each having an upper end connected to one of the I/O pads 130 and a bottom end exposed on the back side 100b of the substrate 100; (e) a solder mask 150 which can be optionally formed over the front side 100a of the substrate 100 while exposing the ground ring 110, the first and second power rings 120, 123, and the I/O pads 130; (f) a semiconductor die 160 having for example, inner bond pads 161 and outer bond pads 162, and which is mounted on the front side 100a of the substrate 100 within the area surrounded by the ground ring 110 and the power rings 120, 123; (g) a set of bonding wires 170, including a subset of bonding wires 171 for connecting the chip's outer bond pads 162 to the various rings 110, 120, 123, 130 and another subset of bonding wires 172 for connecting the chip's inner bonding pads 161 to the substrate's I/O pads 130; and (h) a ball grid array (an array of solder balls) 180 provided on the back side 100b of the substrate 100, which includes a subgroup of ground balls 181 bonded to the ground vias 141; a subgroup of first power balls 182 bonded to the first power vias 142; a subgroup of second power balls 183 bonded to the second power vias 143; and a sub-group of I/O balls 184 bonded to the I/O vias 144. When this BGA package is mounted on an external PCB (not shown), it allows the ground balls 181, the power balls 182, 183, and the I/O balls 184 to be coupled respectively to the PCB's VSS (ground line), VDD (system power(s)), and I/O (signal input/output) lines.
FIG. 1B is a simplified schematic plan view of a similar BGA package. Looking down on the substrate 100, the die 160, the ground ring 100, the first and second power rings 120, 123, and I/O bond fingers 130 (bond pads) and associated traces 131 are all well indicated. In the depicted schematic view, chip inner 161 and outer 162 bond pads are shown with exemplar bond wires 170 (e.g., 171, 172) connecting to associated ones of the first and second power rings 120, 123, ground ring 110, and the I/O pads 130.
Conventionally, the foregoing power/ground ring layout scheme on BGA package can be implemented in many various ways.
Another such example layout is depicted in FIG. 2, which is a schematic plan view of another simplified implementation of a BGA package. A semiconductor die 160 is mounted on the substrate 201. The substrate 201 includes a ground line 210; an inner power line 220 (which provides voltage VDD1); and four outer power lines 231, 232, 233, 234 (which can be used to provide voltages VDD2; VDD3; VDD4; VDD5, respectively). Also provided are traces 240 which are connected to I/O lines. All of these lines and traces can be connected to vias which are connected to back side mounted solder balls. This conventional implementation can supply, at most, five voltages through the power lines (220, 231,232, 233, 234).
Systems requiring more input voltages must make use of the I/O lines to supply these voltages. This has a number of significant disadvantages. First, each I/O line used as a voltage supply line cuts down on the I/O lines available to provide system functionality thereby limiting the usefulness of the final packaged chip. This is especially so when 20, 30, or even 40, or more voltages are required by the systems one the chip. This is becoming more of an issue in modern chip packaging due to the need to isolate more and more different system buses on the chip. Common power sources increase problems with cross over noise between the same busses sharing the same power lines. Thus, there are advantages to be gained by providing separate power voltages. The old method of sacrificing I/O lines suffers from many increasingly significant drawbacks. For example, another disadvantage inherent in using I/O signal traces is the comparatively high impedance caused by narrow line widths of most of these traces.
Thus, what is needed is a method and package for an integrated circuit device that can provide many independent power lines. Especially, advantageous are implementations capable of providing 32 or more separate voltage sources without sacrificing the I/O pin count in the package. Additionally, it would be advantageous if such method and package could provide reduced impedance relative to the impedance experienced by most signal traces used as voltage sources. Also, it is advantageous if such method and package can be configured to isolate switching noise in the power rails for different I/O busses. Moreover, such a method and package would be advantageous if it could be manufactured using standard fabrication technologies currently used to manufacture, for example, current two and four layer PBGA packages.